The Potential of 3D NAND Technology

The demand for NAND flash, a type of non-volatile storage device, has been increasing ever since the first iPod launched, especially as the market for smartphones, tablets, and other electronic gadgets is increasing.

The current iteration of NAND technology, called planar or 2D NAND, is projected to reach its limits soon: as process nodes dip below 20 nm and on the path towards 10 nm, scaling of 2D NAND technology is becoming more difficult as physical constraints begin to affect the performance of the basic memory cell design. 

2D NAND technology has yet to reach an actual limit, but it is only a matter of time before it does, so since the current technology being used will soon hit a wall, a more powerful, a next generation iteration called 3D NAND technology is already being worked on by leading electronics companies and memory chipmakers.

Samsung has already announced its 3D NAND technology in the form of a 24-layer, 128 GB chip; Micron and SK Hynix will follow suit in 2014, while other companies, such as Sandisk, are all working on 3D NAND technology.

The memory cells in 3D NAND devices are stacked on top of each other, in contrast to the 2D horizontal grid design in 2D NAND technology.

Moreover, 3D NAND also holds the promise of vertical scaling because can have string heights of more than 128 bits as compared to current 16-bit-tall strings, but in spite of its potential and the announcement by leading companies in the industry, mass production of 3D NAND technology is challenging. 

Jim Handy, from Objective Analysis, stated that the issue with 3D NAND is its complexity: 3D NAND technology does not require cutting-edge lithography, leading to lower manufacturing costs as compared to extended 2D NAND.

However, the vertical scaling component of the manufacturing process would require high aspect ratio holes, which would in turn require new deposition and etching technologies.

Chipmakers are still trying to extend the potential of 2D NAND for the time being, given the cost and production issues surrounding 3D NAND. Memory chipmakers discussed the issues surrounding 3D NAND technology in a December 2013 forum organized and sponsored by Applied Materials, a semiconductor industry equipment manufacturer. Ritu Shrivastava, Vice President Technology Development, at Sandisk Corporation, said that 2D NAND is still more cost-effective than 3D NAND and that 3D NAND is not yet proven in volume manufacturing, although he also adds that 2D and 3D can coexist for the rest of the decade.

Chuck Dennison, Senior Director Process Integration of Micron, presented their current 16 nm 2D NAND technology that can hold up to 128 GB of data and said that the company plans on a 256 GB class of NAND memory as the next step to 3D NAND. 

Finally, Applied Materials outlined some insights regarding the manufacturing process for the more complex structures needed for constructing 3D NAND device architectures. But for the long term, even if significant challenges remain, the best combination of cost, power, and performance will be found in 3D NAND architectures.

About the author– This article is contributed by MartiniTech Inc., a nanotechnology company based in Tokyo, Japan and specialized in sputtering and thin-film deposition, nanoimprint mold and replica, MEMS design and MEMS foundry services and patterned sapphire substrates for LED applications.